Garbled EDA: Privacy-Preserving Electronic Design Automation
Designed a framework to run chip design tools securely without revealing proprietary IP, using cryptographic multiparty computation.
Hardware security research from my time at the University of Florida. The full list is on Google Scholar.
Designed a framework to run chip design tools securely without revealing proprietary IP, using cryptographic multiparty computation.
Built and hardened protocols that prevent unauthorized cloning of chips, using oblivious transfer cryptography.
Developed a hardware framework that lets neural networks run securely on FPGAs without leaking information through power/timing channels.